The invention relates to semiconductor fabrication, and in particular to mask-alignment test structures for measuring the alignment of superimposed elements formed on and within a semiconductor layer.
Most semiconductor devices are built up using a number of material layers. Each layer is patterned to add or remove selected portions to form circuit features that will eventually make up a complete integrated circuit. The patterning process, known as photolithography, defines the dimensions of the circuit features.
The goal of the patterning process is to create circuit features in the exact dimensions required by the circuit design and to place them in the proper locations on the surface of a semiconductor wafer. Perfect alignment is an ideal that cannot be achieved in practice. Instead, the various layers of an integrated circuit will be misaligned to some extent. Such misalignment is termed xe2x80x9cmask misalignmentxe2x80x9d because misaligned mask images are the source of the error. When circuits fail during fabrication, it is desirable to determine whether the source of the failure is incorrect mask alignment.
There are a number of conventional methods of detecting mask misalignment. For example, U.S. Pat. No. 5,770,995 to Masayuki Kamiya describes a structure that identifies misalignment between a conductive layer and a contact window layer. The disclosed structure indicates the direction of mask misalignment but does not provide an accurate measure of the extent of misalignment. Each of U.S. Pat. No. 4,386,459 to David Boulin and U.S. Pat. No. 4,571,538 to Pei-Ming Chow describe structures that indicate both the direction and extent of mask misalignment. However, the disclosed structures rely upon process-sensitive circuit parameters to produce accurate misalignment data. For example, misalignment data provided by both the Boulin and Chow structures is sensitive to line-width and resistivity variations. There is therefore a need for a mask-alignment detection structure that accurately indicates the direction and extent of mask misalignment, despite process variations.
The above-mentioned U.S. Patents provide useful background information, and are therefore incorporated herein by reference.
The present invention satisfies the need for an accurate mask-alignment detection structure that measures both the direction and extent of misalignment between layers of an integrated circuit. Measurements taken using structures in accordance with the invention are relatively insensitive to process variations, and the test structures can be formed along with other features on an integrated circuit using standard processes.
One embodiment of the invention may be used to measure misalignment between a conductive layer and a contact layer. A first conductive layer is patterned to create a number of IC circuit features, including one conductive element for use in mask alignment. An adjacent insulating layer is patterned to create contact windows through which electrical contact is established with the underlying (over overlying) conductive layer. The insulating layer is patterned so that at least one resistive element formed within a contact window only partially overlaps the underlying conductive element. The overlap area, or xe2x80x9ccontact area,xe2x80x9d is proportional to the extent to which the contact window is aligned with the conductive element in a first dimension, but is relatively independent of the extent to which the contact window is aligned with the conductive element in a second dimension perpendicular to the first. The resistance of the resistive element varies with contact area, the resistance increasing as the contact area decreases. Thus, the resistance of the resistive element is proportional to the extent of misalignment in the first dimension, and may therefore be used to measure misalignment in that dimension.
In one embodiment, the resistive element is sandwiched between the conductive element and a second conductive element formed from a second conductive layer. The resistance of the resistive element is then measured by forcing a constant current through the resistive element and measuring the resulting voltage drop. (Alternatively, the resistance can be determined by presenting a constant voltage across the resistive element and measuring the resulting current.) The resistance of the resistive element is then converted into an approximation of misalignment between the contact layer and the first conductive layer.
Process variations can affect the resistance of the resistive element, and therefore the validity of the measure of misalignment. Another embodiment of the invention addresses this problem using a second mask-alignment detection structure mirroring the structure described above. The second structure is opposite but otherwise identical to the first. Consequently, misalignment that increases the resistance through the first structure reduces the resistance through the second structure. The misalignment is then calculated using the relationship between the two resistances. One embodiment includes more than one pair of mirror-image detection structures, each exhibiting different degrees of overlap. This embodiment provides additional data points from which to discern misalignment.
The first embodiment of the invention measures the alignment between a conductive layer and a contact layer. Alignment between other types of circuit layers is equally important. Thus, one embodiment of the invention measures misalignment between diffusion regions and conductors, and yet another embodiment measures misalignment between diffusion regions and windows through which other diffusion regions are to be formed. Each embodiment employs variable resistances as a measure of misalignment, and can be formed using conventional processing techniques.
Test structures in accordance with the invention can include many resistive elements, and semiconductor wafers might include many test structures. Unfortunately, the test terminals of these structures collectively occupy a great deal of valuable area. An embodiment of the invention addresses this problem with a test circuit that reduces the requisite number of test terminals using row and column decoders that independently select each resistive element from an array of test structures.
This summary does not purport to define the invention The invention is defined by the claims.